Texas Instruments SN74LVC07AD Buffer & Line Driver, Open Drain, 14-Pin SOIC
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Driver
Input Type
Single Ended
Output Type
Open Drain
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
14
Maximum Low Level Output Current
24mA
Maximum Propagation Delay Time @ Maximum CL
3.6 ns @ 3.3 V
Dimensions
8.65 x 3.91 x 1.58mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC Family Inverters & Buffers, Texas Instruments
Texas Instruments range of Inverters and Buffers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
P.O.A.
Each (In a Tube of 50) (Exc. Vat)
50
P.O.A.
Each (In a Tube of 50) (Exc. Vat)
50
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Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Driver
Input Type
Single Ended
Output Type
Open Drain
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
14
Maximum Low Level Output Current
24mA
Maximum Propagation Delay Time @ Maximum CL
3.6 ns @ 3.3 V
Dimensions
8.65 x 3.91 x 1.58mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC Family Inverters & Buffers, Texas Instruments
Texas Instruments range of Inverters and Buffers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family