Τεχνικό φυλλάδιο
Προδιαγραφές
Brand
NexperiaLogic Family
HC
Logic Function
D Type
Input Type
Single Ended
Output Type
3 State
Output Signal Type
Single Ended
Triggering Type
Positive Edge
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
16
Set/Reset
Master Reset
Number of Elements per Chip
4
Maximum Propagation Delay Time @ Maximum CL
175 ns @ 2 V
Maximum Operating Supply Voltage
6 V
Dimensions
10 x 4 x 1.45mm
Maximum Operating Temperature
+125 °C
Propagation Delay Test Condition
50pF
Length
10mm
Height
1.45mm
Width
4mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
2 V
Χώρα Προέλευσης
Thailand
Λεπτομέρειες Προϊόντος
74HC Family Flip-Flops & Latches, Nexperia
A range of NXP Flip-Flops and Latches from the 74HC Family of CMOS Logic ICs. The 74HC Family use silicon gate CMOS technology to achieve operating speeds similar to the LSTTL family but with the low power consumption of standard CMOS integrated circuits.
74HC Family
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Παρακαλούμε ελέγξτε ξανά αργότερα.
€ 0,60
Μονάδας (Σε μία ράγα των 50) (Exc. Vat)Χωρίς Φ.Π.Α
€ 0,744
Μονάδας (Σε μία ράγα των 50) Με Φ.Π.Α
50
€ 0,60
Μονάδας (Σε μία ράγα των 50) (Exc. Vat)Χωρίς Φ.Π.Α
€ 0,744
Μονάδας (Σε μία ράγα των 50) Με Φ.Π.Α
50
Τεχνικό φυλλάδιο
Προδιαγραφές
Brand
NexperiaLogic Family
HC
Logic Function
D Type
Input Type
Single Ended
Output Type
3 State
Output Signal Type
Single Ended
Triggering Type
Positive Edge
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
16
Set/Reset
Master Reset
Number of Elements per Chip
4
Maximum Propagation Delay Time @ Maximum CL
175 ns @ 2 V
Maximum Operating Supply Voltage
6 V
Dimensions
10 x 4 x 1.45mm
Maximum Operating Temperature
+125 °C
Propagation Delay Test Condition
50pF
Length
10mm
Height
1.45mm
Width
4mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
2 V
Χώρα Προέλευσης
Thailand
Λεπτομέρειες Προϊόντος
74HC Family Flip-Flops & Latches, Nexperia
A range of NXP Flip-Flops and Latches from the 74HC Family of CMOS Logic ICs. The 74HC Family use silicon gate CMOS technology to achieve operating speeds similar to the LSTTL family but with the low power consumption of standard CMOS integrated circuits.