Τεχνικό φυλλάδιο
Προδιαγραφές
Brand
onsemiProduct Type
18 Bit D Type Latch
Logic Family
4000
Latch Mode
Transparent
Logic Function
RS-Latch
Number of Channels
4
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface
Minimum Supply Voltage
-5V
Package Type
SOIC
Pin Count
16
Maximum Supply Voltage
18V
Minimum Operating Temperature
-55°C
Maximum Operating Temperature
125°C
Length
10mm
Height
1.5mm
Standards/Approvals
No
Series
4000B
Automotive Standard
AEC-Q100
Λεπτομέρειες Προϊόντος
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.
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Ημερομηνία αποθέματος προσωρινά μη διαθέσιμη
€ 26,40
€ 0,55 Μονάδας (Σε μία ράγα των 48) (Exc. Vat)Χωρίς Φ.Π.Α
€ 32,74
€ 0,682 Μονάδας (Σε μία ράγα των 48) Με Φ.Π.Α
48
€ 26,40
€ 0,55 Μονάδας (Σε μία ράγα των 48) (Exc. Vat)Χωρίς Φ.Π.Α
€ 32,74
€ 0,682 Μονάδας (Σε μία ράγα των 48) Με Φ.Π.Α
Ημερομηνία αποθέματος προσωρινά μη διαθέσιμη
48
| Quantity Ποσότητα | Τιμή μονάδας | Per Ράγα |
|---|---|---|
| 48 - 432 | € 0,55 | € 26,40 |
| 480 - 912 | € 0,42 | € 20,16 |
| 960+ | € 0,37 | € 17,76 |
Ideate. Create. Collaborate
JOIN FOR FREE
No hidden fees!
Τεχνικό φυλλάδιο
Προδιαγραφές
Brand
onsemiProduct Type
18 Bit D Type Latch
Logic Family
4000
Latch Mode
Transparent
Logic Function
RS-Latch
Number of Channels
4
Output Type
3 State
Polarity
Non-Inverting
Mount Type
Surface
Minimum Supply Voltage
-5V
Package Type
SOIC
Pin Count
16
Maximum Supply Voltage
18V
Minimum Operating Temperature
-55°C
Maximum Operating Temperature
125°C
Length
10mm
Height
1.5mm
Standards/Approvals
No
Series
4000B
Automotive Standard
AEC-Q100
Λεπτομέρειες Προϊόντος
The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input, a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.
Ideate. Create. Collaborate
JOIN FOR FREE
No hidden fees!
